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Table 12. Register Address Map
TRANSIENT_THS (1)(3)
R/W
0x1F
0x20
00000000
0x00
Transient event threshold
TRANSIENT_COUNT
(1)(3)
R/W
0x20
0x21
00000000
0x00
Transient debounce counter
PULSE_CFG (1)(4)
PULSE_SRC (1)(2)
R/W
R
0x21
0x22
0x22
0x23
00000000
00000000
0x00
0x00
ELE, Double_XYZ or Single_XYZ
EA, Double_XYZ or Single_XYZ
PULSE_THSX
PULSE_THSY
(1)(3)
(1)(3)
R/W
R/W
0x23
0x24
0x24
0x25
00000000
00000000
0x00
0x00
X pulse threshold
Y pulse threshold
PULSE_THSZ (1)(4)
R/W
0x25
0x26
00000000
0x00
Z pulse threshold
PULSE_TMLT
(1)(4)
R/W
0x26
0x27
00000000
0x00
Time limit for pulse
PULSE_LTCY
(1)(4)
PULSE_WIND (1)(4)
ASLP_COUNT (1)(4)
CTRL_REG1 (1)(4)
CTRL_REG2 (1)(4)
CTRL_REG3 (1)(4)
CTRL_REG4 (1)(4)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
00000000
00000000
00000000
00000000
00000000
00000000
00000000
0x00
0x00
0x00
0x00
0x00
0x00
0x00
Latency time for 2 nd pulse
Window time for 2nd pulse
Counter setting for Auto-SLEEP
ODR = 800 Hz, STANDBY Mode.
Sleep Enable, OS Modes,
RST, ST
Wake from Sleep, IPOL, PP_OD
Interrupt enable register
CTRL_REG5
(1)(4)
R/W
0x2E
0x2F
00000000
0x00
Interrupt pin (INT1/INT2) map
OFF_X (1)(4)
R/W
0x2F
0x30
00000000
0x00
X-axis offset adjust
OFF_Y
(1)(4)
R/W
0x30
0x31
00000000
0x00
Y-axis offset adjust
OFF_Z
(1)(4)
R/W
0x31
0x0D
00000000
0x00
Z-axis offset adjust
Reserved (do not modify)
0x40 – 7F
—
—
—
Reserved. Read return 0x00.
1. Register contents are preserved when transition from ACTIVE to STANDBY mode occurs.
2. Register contents are reset when transition from STANDBY to ACTIVE mode occurs.
3. Register contents can be modified anytime in STANDBY or ACTIVE mode. A write to this register will cause a reset of the corresponding
internal system debounce counter.
4. Modification of this register’s contents can only occur when device is STANDBY mode except CTRL_REG1 ACTIVE bit and CTRL_REG2 RST
bit.
Note : Auto-increment addresses which are not a simple increment are highlighted in bold . The auto-increment addressing is only enabled when
device registers are read using I 2 C burst read mode. Therefore the internal storage of the auto-increment address is cleared whenever a
stop-bit is detected.
6.1
Data Registers
The following are the data registers for the MMA8451Q. For more information on data manipulation of the MMA8451Q, refer
to application note, AN4076 .
When the F_MODE bits found in Register 0x09 (F_SETUP), bits 7 and 6 are both cleared (the FIFO is not on). Register 0x00
reflects the real-time status information of the X, Y and Z sample data. When the F_MODE value is greater than zero the FIFO
is on (in either Fill, Circular or Trigger mode). In this case Register 0x00 will reflect the status of the FIFO. It is expected when the
FIFO is on that the user will access the data from Register 0x01 (X_MSB) for either the 14-bit or 8-bit data. When accessing the
8-bit data the F_READ bit (Register 0x2A) is set which modifies the auto-incrementing to skip over the LSB data. When F_READ
bit is cleared the 14-bit data is read accessing all 6 bytes sequentially (X_MSB, X_LSB, Y_MSB, Y_LSB, Z_MSB, Z_LSB).
F_MODE = 00: 0x00 STATUS: Data Status Register (Read Only)
Bit 7
ZYXOW
Bit 6
ZOW
Bit 5
YOW
Bit 4
XOW
Bit 3
ZYXDR
Bit 2
ZDR
Bit 1
YDR
Bit 0
XDR
MMA8451Q
Sensors
20
Freescale Semiconductor, Inc.
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相关代理商/技术参数
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